The present invention generally relates to a sequential access memory for use as a data delaying device in a digital circuit.
Generally, an arrangement as referred to in FIG. 5 is provided as a sequential access memory. The sequential access memory is adapted for inputting an input signal string composed of an a portion having m words of data and a b portion having l words of data as shown in FIG. 4(1), and for outputting an output signal string delayed from the input signal string by two units in the a portion and one unit in the b portion as shown in FIG. 4(2).
In FIG. 5, the a-portion two-unit delaying device 51 is composed of an m.times.2-words memory 52 having a memory capacity of m.times.2-words and a modulo m.times.2 counter 53 for effecting the modulo m.times.2 counting. A b-portion one-unit delaying device 55 is composed of an l-word memory 56 having a memory capacity of l words and an modulo l counter 57 for effecting the modulo l counting.
The modulo m.times.2 counter 53 and the modulo l counter 57 respectively have a clock input 53a and a clock input 57a, a count enable termlinal 53b and a count enable terminal 57b. The a/b switching input is connected to the count enable terminals 53b and 57b. When the a/b switch input is at the a portion, the clock is input into the clock input 53a. The modulo m.times.2 counter 53 counts up by the input of the clock to output the address into the m.times.2-words memory 52. When the a/b switch input is at the b portion, the clock is input into the clock input 57a. The modulo l counter 57 counts up by the input of the clock to output the address into the l-word memory 56.
The m.times.2-words memory 52 and the l-word memory 56 respectively receive the addresses from the modulo m.times.2 counter 53 and the modulo l counter 57 for reading and storing the data in the address. Namely, the modulo m.times.2 counter 53 and the modulo l counter 57 are commonly used for reading and storing, and the reading and storing are effected at the same time. But data that is one time old are read, instead of the data to be stored at that time. Accordingly, the data stored in a certain address of the memory 52 is read from the a portion when the modulo m.times.2 counter 53 comes back to the same address again, which requires the m.times.2 clocks. The l number of clocks are required by the b portion. The data read from the m.times.2-words memory 52 and the l-word memory 56 are to be outputted through an output switching device 58. The a/b switching input is connected to the output switching device 58. When the a/b switching input is at the a portion, the data from the m.times. 2-words memory 52 are outputted through the output switching device 58. When the a/b switching input is at the b portion, the data of the l-word memory 56 is outputted through the output switching device 58.
The data stored in a certain address of the m.times.2-words memory 52 are read when the modulo m.times.2 counter 53 has accessed the address of the address again, but the m.times.2 clocks are required for the storing of the data to the reading thereof. As the counter 53 for accessing the address of the memory 52 is 2.times.m-base when the a portion has the m words, the modulo m.times.2 counter 53 is not operated while the a/b switching input is at the b portion, so that the data of the a portion are delayed by two units before being outputted. The l-number of clocks are required, in a certain address of the l-word memory 56, from the loading of the data to the reading of the data. When the b portion is the l-word, the counter 57 for accessing the address of the memory 56 is l-base. While the a/b switch input is at the a portion, the modulo l counter 57 is not operated, so that the data of the b portion are delayed by one unit before being outputted.
In the manner described aboved the input signal string shown in FIG. 4(1) is delayed, and may be outputted as the output signal string shown in FIG. 4(2).
However, the conventional sequential access memory respectively requires a separate memory and a separate counter for the data of the a portion and the data of the b portion. Also, an output switching device for switching the output of the two memories is required, which cause the circuit be become complicated and expensive.